View CY7C341B-35HI_8864198.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

192-macrocell max ? epld cy7c341b cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03016 rev. *b revised december 28, 2002 341b features ? 192 macrocells in 12 logic array blocks (labs) eight dedicated inputs, 64 bidirectional i/o pins advanced 0.65-micron cmos technology to increase performance programmable interconnect array 384 expander product terms available in 84-pin hlcc, plcc, and pga packages functional description the cy7c341b is an erasable programmable logic device (epld) in which cmos eprom cells are used to configure logic functions within the device. the max ? architecture is 100% user-configurable, allowing the devices to accom- modate a variety of independent logic functions. the 192 macrocells in the cy7c341b are divided into 12 logic array blocks (labs), 16 per lab. there are 384 expander product terms, 32 per lab, to be used and shared by the macrocells within each lab. each lab is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. the speed and density of the cy7c341b allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series ttl logic, to complex controllers and multifunction chips. with greater than 37 times the functionality of 20-pin plds, the cy7c341b allows the replacement of over 75 ttl devices. by replacing large amounts of logic, the cy7c341b reduces board space, part count, and increases system reliability. each lab contains 16 macrocells. in labs a, f, g, and l, 8 macrocells are connected to i/o pins and eight are buried, while for labs b, c, d, e, h, i, j, and k, four macrocells are connected to i/o pins and 12 are buried. moreover, in addition to the i/o and buried macrocells, there are 32 single product term logic expanders in each lab. their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell. logic array blocks there are 12 logic array blocks in the cy7c341b. each lab consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an i/o block. the lab is fed by the programmable interconnect array and the dedicated input bus. all macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. expanders feed themselves and the macrocell array. all i/o feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other labs as well as the macro- cells in the lab in which they are situated. externally, the cy7c341b provides eight dedicated inputs, one of which may be used as a system clock. there are 64 i/o pins that may be individually configured for input, output, or bidirectional data flow. programmable interconnect array the programmable interconnect array (pia) solves inter- connect limitations by routing only the signals needed by each logic array block. the inputs to the pia are the outputs of every macrocell within the device and the i/o pin feedback of every pin on the device. unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the pia has a fixed delay. this eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. the fixed delay, regardless of programmable interconnect array config- uration, simplifies design by assuring that internal signal skews or races are avoided. the result is ease of design imple- mentation, often in a single pass, without the multiple internal logic placement and routing iterations required for a program- mable gate array to achieve design timing objectives. design recommendations for proper operation, input and output pins must be constrained to the range gnd < (v in or v out ) < v cc . unused inputs must always be tied to an appropriate logic level (either v cc or gnd). each set of v cc and gnd pins must be connected together directly at the device. power supply decoupling capacitors of at least 0.2 f must be connected between v cc and gnd. for the most effective decoupling, each v cc pin should be separately decoupled to gnd, directly at the device. decoupling capacitors should have good frequency response, such as monolithic ceramic types. 400 300 200 100 1 khz 10 khz 100 khz 1 mhz i cc maximum frequency 10 mhz 0 50 mhz 100 hz active (ma) typ. v cc = 5.0v room temp. typical i cc vs. f max selection guide 7c341b-25 7c341b-35 unit maximum access time 25 35 ns
cy7c341b document #: 38-03016 rev. *b page 2 of 11 design security the cy7c341b contains a programmable design security feature that controls the access to the data programmed into the device. if this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. this enables a high level of design control to be obtained since programmed data within eprom cells is invisible. the bit that controls this function, along with all other program data, may be reset simply by erasing the device. the cy7c341b is fully functionally tested and guaranteed through complete testing of each programmable eprom bit and all internal logic elements thus ensuring 100% programming yield. the erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. the devices also contain on-board logic test circuitry to allow verification of function and ac specification once encapsu- lated in non-windowed packages. 01 2 3 4 i output current (ma) typical v o output voltage (v) 250 200 150 100 50 5 o i oh i ol v cc = 5.0v room temp. output drive current p i a macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 7 macrocell 8 macrocell97 macrocell98 macrocell99 macrocell 100 macrocell 101 macrocell 102 macrocell 103 macrocell 104 macrocell 9 ? 16 macrocell 105 ? 112 macrocell 17 macrocell 18 macrocell 19 macrocell 20 macrocell 113 macrocell 114 macrocell 115 macrocell 116 macrocell 21 ? 32 macrocell 117 ? 128 macrocell 33 macrocell 34 macrocell 35 macrocell 36 macrocell 129 macrocell 130 macrocell 131 macrocell 132 macrocell 37 ? 48 macrocell 133 ? 144 macrocell 49 macrocell 50 macrocell 51 macrocell 52 macrocell 145 macrocell 146 macrocell 147 macrocell 148 macrocell 53 ? 64 macrocell 149 ? 160 macrocell 65 macrocell 66 macrocell 67 macrocell 68 macrocell 161 macrocell 162 macrocell 163 macrocell 164 macrocell 69 ? 80 macrocell 165 ? 176 macrocell 81 macrocell 82 macrocell 83 macrocell 84 macrocell 85 macrocell 86 macrocell 87 macrocell 88 macrocell 177 macrocell 178 macrocell 179 macrocell 180 macrocell 181 macrocell 182 macrocell 183 macrocell 184 macrocell 89 ? 96 macrocell 185 ? 192 input (c6) 84 input (c7) 83 input (l7) 44 input (j7) 43 1 (a6) input/clk 2(a5) input 41 (k6) input 42 (j6) input 4(c5) 5(a4) 6(b4) 7(a3) 8(a2) 9(b3) 10 (a1) 11 (b2) 12 (c2) 13 (b1) 14 (c1) 15 (d2) 16 (d1) 17 (e3) 20 (f2) 21 (f3) 22 (g3) 23 (g1) 25 (f1) 26 (h1) 27 (h2) 28 (j1) 29 (k1) 30 (j2) 31 (l1) 32 (k2) 33 (k3) 34 (l2) 35 (l3) 36 (k4) 37 (l4) 38 (j5) 46 (l6) 47 (l8) 48 (k8) 49 (l9) 50 (l10) 51 (k9) 52 (l11) 53 (k10) 54 (j10) 55 (k11) 56 (j11) 57 (h10) 58 (h11) 59 (f10) 62 (g9) 63 (f9) 64 (f11) 65 (e11) 67 (e9) 68 (d11) 69 (d10) 70 (c11) 71 (b11) 72 (c10) 73 (a11) 74 (b10) 75 (b9) 76 (a10) 77 (a9) 78 (b8) 79 (a8) 80 (b6) system clock 3, 24, 45, 66 (b5, g2, k7, e10) 18, 19, 39, 40, 60, 61, 81, 82 (e1, e2, k5, l5, g10, g11, a7, b7) v cc gnd () ? pertain to 84-pin pga package lab a lab b lab c lab d lab e lab f lab g lab h lab i lab j lab k lab l logic block diagram
cy7c341b document #: 38-03016 rev. *b page 3 of 11 pin configurations i/o top view plcc/hlcc 9 8 6 7 5 13 14 12 11 10 49 48 58 59 60 23 24 26 25 27 15 16 47 46 43 28 33 20 21 19 18 17 22 34 35 37 36 38 39 42 41 43 44 45 40 66 65 63 64 62 61 v cc 7c341b 67 68 69 74 72 73 71 70 84 83 81 82 80 21 79 i/o input i/o input/clk input input gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o v cc v cc input gnd gnd input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc input input/ clk gnd i/o i/o i/o i/o v cc i/o i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc input i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc i/o i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o pga bottom view 7c341b input gnd i/o i/o i/o i/o i/o i/o i/o l k j h g f e d c b a 123456 78910 11 i/o i/o i/o i/o i/o input input input input i/o i/o i/o i/o i/o i/o i/o i/o 53 52 51 50 30 29 31 32 i/o i/o i/o i/o i/o i/o i/o i/o 54 55 56 57 i/o i/o i/o i/o 77 78 76 75 i/o i/o i/o i/o i/o gnd input input gnd i/o figure 1. cy7c341b internal timing model logic array control delay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in pia delay t pia register output delay t od t xz t zx logic array delay t lad logic array delay t fd i/o delay t io input/ output input system clock delay t ics t rh t rsu t pre t clr
cy7c341b document #: 38-03016 rev. *b page 4 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .......................................? 65 c to +135 c ambient temperature with power applied.............................................. ? 65 c to +135 c maximum junction temperature (under bias)................................................................. 150 c supply voltage to ground potential [1] ..............? 2.0v to +7.0v dc output current, per pin [1] ..................... ? 25 ma to +25 ma dc input voltage [1] ................................................? 2.0v to +7.0v operating range [3] range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 10% electrical characteristics over the operating range parameter description test conditions min. max. unit v cc output high voltage maximum v cc rise time is 10 ms 4.75(4.5) 5.25(5.5) v v oh output high voltage v cc = min., i oh = ? 4.0 ma [2] 2.4 v v ol output low voltage v cc = min., i ol = 8 ma [2] 0.45 v v ih input high level 2.0 v cc + 0.3 v v il input low level ? 0.3 0.8 v i ix input current gnd v in v cc ? 10 +10 a i oz output leakage current v o = v cc or gnd ? 40 +40 a t r (recommended) input rise time 100 ns t f (recommended) input fall time 100 ns capacitance parameter description test conditions max. unit c in input capacitance v in = 0v, f = 1.0 mhz 10 pf c out output capacitance v out = 0v, f = 1.0 mhz 20 pf ac test loads and waveforms notes: 1. minimum dc input is ? 0.3v. during transactions, input may undershoot to ? 2.0v or overshoot to 7.0v for input currents less then 100 ma and periods shorter than 20 ns. 2. the i oh parameter refers to high-level ttl output current; the i ol parameter refers to low-level ttl output current. 3. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 3.0v 5v output r1 464 ? r2 250 ? 50 pf including jig and scope gnd 90% 10% 90% 10% < 6ns <6 ns 5v output r1 464 ? r2 250 ? (a) (b) output 1.75v equivalent to: th venin equivalent (commercial/military) c341b-7 c341b-8 all input pulses t r t f 5pf 163 ?
cy7c341b document #: 38-03016 rev. *b page 5 of 11 external switching characteristics over the operating range parameter description 7c341b-25 7c341b-35 unit min. max min. max t pd1 dedicated input to combinatorial output delay [4] commercial 25 35 ns t pd2 i/o input to combinatorial output delay [4] commercial 40 55 ns t su global clock set-up time commercial 15 25 ns t co1 synchronous clock input to output delay [4] commercial 14 20 ns t h input hold time from synchronous clock input commercial 0 0 ns t wh synchronous clock input high time commercial 8 12.5 ns t wl synchronous clock input low time commercial 8 12.5 ns f max maximum register toggle frequency [5] commercial 62.5 40.0 mhz t aco1 dedicated asynchronous clock input to output delay [4] commercial 25 35 ns t as1 dedicated input or feedback set-up time to asynchronous clock input commercial 5 10 ns t ah input hold time from asynchronous clock input commercial 6 10 ns t awh asynchronous clock input high time [6] commercial 11 16 ns t awl asynchronous clock input low time [6] commercial 9 14 ns t cnt minimum global clock period commercial 20 30 ns t odh output data hold time after clock commercial 2 2 ns f cnt maximum internal global clock frequency [7] commercial 50 33.3 mhz t acnt minimum internal array clock frequency commercial 20 30 ns f acnt maximum internal array clock frequency [7] commercial 50 33.3 mhz notes: 4. c1 = 35 pf. 5. the f max values represent the highest frequency for pipeline data. 6. this parameter is measured with a positive-edge-triggered clock at the register. for negative-edge clocking, the t ach and t acl parameter must be swapped. 7. this parameter is measured with a 16-bit counter programmed into each lab.
cy7c341b document #: 38-03016 rev. *b page 6 of 11 internal switching characteristics over the operating range parameter description 7c341b-25 7c341b-35 unit min. max min. max t in dedicated input pad and buffer delay commercial 5 11 ns t io i/o input pad and buffer delay commercial 6 11 ns t exp expander array delay commercial 12 20 ns t lad logic array data delay commercial 12 14 ns t lac logic array control delay commercial 10 13 ns t od output buffer and pad delay [4] commercial 5 6 ns t zx output buffer enable delay [4] commercial 10 13 ns t xz output buffer disable delay [8] commercial 10 13 ns t rsu register set-up time relative to clock signal at register commercial 6 12 ns t rh register hold time relative to clock signal at register commercial 4 8 ns t latch flow-through latch delay commercial 3 4 ns t rd register delay commercial 1 2 ns t comb transparent mode delay commercial 3 4 ns t ic asynchronous clock logic delay commercial 14 16 ns t ics synchronous clock delay commercial 3 1 ns t fd feedback delay commercial 1 2 ns t pre asynchronous register preset time commercial 5 7 ns t clr asynchronous register clear time commercial 5 7 ns t pia programmable interconnect array delay commercial 14 20 ns note: 8. c1 = 5 pf.
cy7c341b document #: 38-03016 rev. *b page 7 of 11 switching waveforms external combinatorial dedicated input/ i/o input combinatorial output t pd1 /t pd2 t wl t su t h t wh external synchronous clock at register synchronous synchronous logic array data from registered clock pin outputs t co1 external asynchronous t ah t as1 t awh t awl dedicated inputs or registered feedback asynchronous clock input internal combinatorial t in t t exp t lac ,t lad t comb t od input pin i/o pin logic array logic array output input array delay expander output pin io
cy7c341b document #: 38-03016 rev. *b page 8 of 11 switching waveforms (continued) internal asynchronous t io t awh t awl t f t in t ic t rsu t rh t rd ,t latch t fd t clr ,t pre t fd clock pin logic array logic array clock from data from clock into logic array register output to another lab t pia to local lab register output logic array t r t in t ics t rsu t rh system cl ock pin system clock at register data from logic array internal synchronous t xz t zx t od high impedance state clock from logic array logic array data from output pin t rd internal synchronous ordering information speed (ns) ordering code package name package type operating range 25 cy7c341b-25hc/hi h84 84-lead windowed leaded chip carrier commercial/industrial cy7c341b-25jc/ji j83 84-lead plastic leaded chip carrier cy7c341b-25rc/ri r84 84-lead windowed pin grid array 35 cy7c341b-35hc/hi h84 84-lead windowed leaded chip carrier commercial/industrial cy7c341b-35jc/ji j83 84-lead plastic leaded chip carrier cy7c341b-35rc/ri r84 84-lead windowed pin grid array
cy7c341b document #: 38-03016 rev. *b page 9 of 11 package diagrams 84-leaded windowed leaded chip carrier h84 51-80081
cy7c341b document #: 38-03016 rev. *b page 10 of 11 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. max is a registered trademark of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 51-85006-a 84-lead plastic leaded chip carrier j83 84-lead windowed pin grid array r84 51-80026-*b
cy7c341b document #: 38-03016 rev. *b page 11 of 11 document title: cy7c341b 192-macrocell max ? epld document number: 38-03016 rev. ecn no. issue date orig. of change description of change ** 106316 05/17/01 szv change from ecn #: 38-00137 to 38-03016 *a 113613 04/11/02 oor pga package diagram dimensions were updated *b 122227 12/28/02 rbi power up requirements added to operating range information

▲Up To Search▲

Price & Availability of CY7C341B-35HI

	To Download CY7C341B-35HI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .